The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor wiring require responsive changes in interconnection technology, which is considered one of the most demanding aspects of ultra large scale integration technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnect pattern, particularly wherein submicron vias, contacts and trenches have high aspect ratios due to miniaturization.
Conventional semiconductor devices comprise a semiconductor substrate, normally of monocrystalline silicon, and a plurality of sequentially formed dielectric interlayers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines formed in trench openings typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor "chips" comprising three and four levels of metallization are becoming more prevalent as device geometries shrink to submicron levels.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Thus, the interconnection pattern limits the speed of the integrated circuit.
In ULSI structures, high circuit speeds, high packing density and low powered dissipation are required. Consequently, feature sizes must be scaled down. The interconnect related time delays become the major limitation in achieving high circuit speeds. Shrinking device size automatically miniaturizes the interconnect feature size which increases interconnect resistance and interconnect current densities. Poor step coverage of metal and submicron high aspect ratio via holes also increases interconnect resistance and electromigration failures.
If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases in accordance with submicron design rules, the rejection rate due to integrated circuit speed delays approaches and even exceeds 20%.
One way to increase the control speed of semiconductor circuitry is to reduce the resistance of a conductive pattern. Conventional metallization patterns are typically formed by depositing a layer of conductive material, notably aluminum (Al) or an alloy thereof, and etching, or by damascene techniques wherein trenches are formed in dielectric layers and filled with a conductive material. Excess conductive material on the surface of the dielectric layer is then removed, as by chemical-mechanical polishing. Al is conventionally employed because it is relatively inexpensive, exhibits low resistivity and is relatively easy to etch. However, as the size of openings for vias/contacts and trenches is scaled down to the submicron range, step coverage problems have arisen involving the use of Al which has decreased the reliability of interconnections formed between different wiring layers. Such poor step coverage results in high current density and enhanced electromigration. Moreover, low dielectric constant polyimide materials, when employed as dielectric interlayers, create moisture/bias reliability problems when in contact with Al.
One approach to improved interconnection paths in vias comprises the use of completely filled plugs of a metal, such as W. Accordingly, many current semiconductor devices utilizing VLSI (very large scale integration) technology employ Al for a wiring metal and w plugs for interconnections at different levels. However, the use W is attendant with several disadvantages. For example, most W processes are complex and expensive. Moreover, W has a high resistivity. The Joule heating may enhance electromigration of adjacent Al wiring. Furthermore, W plugs are susceptible to void formation and the interface with the wiring layer usually results in high contact resistance.
Another attempted solution for the Al plug interconnect problem comprises the use of chemical vapor deposition (CVD) or physical vapor deposition (PVD) at elevated temperatures for Al deposition. The use of CVD for depositing Al has proven expensive, while hot PVD Al deposition requires very high process temperatures incompatible with manufacturing integrated circuitry.
Copper (Cu) has recently received considerable attention as a replacement material for Al in VLSI interconnect metallizations. Cu exhibits superior electromigration properties and has a lower resistivity than Al. In addition, Cu has improved electrical properties vis-a-vis W, making Cu a desirable metal for use as a conductive plug as well as conductive wiring. For comparable performance characteristics, aluminum interconnect lines typically exhibit a current density limit of 2.times.10.sup.5 amp/cm.sup.2 ; whereas, a copper line would typically exhibit a current density limit of 5.times.10.sup.6 amp/cm.sup.2. Cu electromigration in interconnect lines has a high activation energy, i.e., up to twice as large as that of Al. Consequently, Cu lines that are significantly thinner than Al lines can theoretically be employed, thereby reducing cross talk and capacitance.
It is expected that a Cu interconnect material leads to an improvement of one and one half times in the maximum clock frequency of a complimentary metal-oxide semiconductor (CMOS) chip vis-a-vis the Al-based interconnects for devices with effective channel ends of about 0.25 .mu.m. Such favorable electrical characteristics of Cu provide an incentive for developing Cu films as interconnect layers in ULSI devices as well top metal layers. However, there are also disadvantages attendant upon the use of Cu. For example, Cu metallization is very difficult to etch. Moreover, Cu readily diffuses through silicon dioxide, the typical dielectric interlayer material employed in the manufacture of semiconductor devices, and adversely affects the devices.
One conventional approach in attempting to form Cu plugs and wiring comprises the use of damascene structures employing chemical mechanical polishing, as in Chow et al., U.S. Pat. No. 4,789,648. However, due to Cu diffusion through dielectric interlayer materials, such as silicon dioxide, Cu interconnect structures must be encapsulated by a diffusion barrier layer. Typical diffusion barrier metals include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium tungsten (TiW), and silicon nitride (Si.sub.3 N.sub.4) for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between Cu and the dielectric interlayer, but includes interfaces with other metals as well.
Electroless deposition has been suggested as a technique for forming interconnect structures. See, for example, "Electroless Cu for VLSI," Cho et al., MRS Bulletin, June 1993, pp. 31-38; "Selective Electroless Metal Deposition For Integrated Circuit Fabrication," Ting et al., J. Electrochem. Soc., 136, 1989, p. 456 et seq.; "Selective Electroless Metal Deposition For Via Hole Filling in VLSI Multilevel Interconnection Structures," Ting et al., J. Electrochem. Soc., 136, 1989, p. 462 et seq.; and Shacham et al., U.S. Pat. No. 5,240,497.
Electroless Cu deposition is attractive due to low processing costs and high quality Cu deposits. In addition, equipment for performing electroless metal deposition is relatively inexpensive vis-a-vis other semiconductor processing equipment for depositing metals. Electroless deposition also offers the advantageous opportunity for batch processing of wafers, thereby further reducing the cost of electroless deposition and increasing production throughput. However, electroless deposition requires a catalytic surface, i.e., seed layer, for the autocatalytic action to occur. See, for example, Baum et al., U.S. Pat. No. 4,574,095 and "Electroless Copper Deposition on Metals and Silicides," Mak, MRS Bulletin, August 1994, pp. 55-62. It is difficult to obtain reliable and reproducible electroless Cu deposition, since the seed layer surface must maintain catalytic activity for effective electroless deposition of Cu.
Copending application Ser. No. 08/587,264, filed Jan. 16, 1996, discloses a method of electrolessly depositing Cu in an interconnect structure, which method comprises initially depositing a barrier layer in an opening, depositing a catalytic seed layer, preferably of Cu, on the barrier layer, and then depositing a protective layer the catalytic layer encapsulating and protecting the catalytic layer from oxidation. The preferred protective material is Al which forms an Al--Cu alloy at the interface of the catalytic and protective layers, thereby encapsulating the underlying Cu. Subsequently, Cu is electrolessly deposited from an electroless deposition solution which dissolves the overlying protective alloy layer to expose the underlying catalytic Cu layer.
As the aspect ratio of contact and via openings, as well as trench openings, approaches 2:1 and greater, it becomes increasingly more challenging to voidlessly fill openings for contacts, vias and trenches of interconnect patterns employing conventional technology, such as magnetron sputtering techniques involving either direct current or radio frequency sputtering. Conventional attempts to improve sputtering capabilities comprise the use of a collimator as in Sandhu et al., U.S. Pat. No. 5,409,587.
A more recent approach in the evolution of high aspect ratio contact/via interconnection technology involves the ionization of sputtered metals by a high density plasma. See S.M. Rossnagel et al., "Metal ion deposition from ionized magnetron sputtering discharge," J. Vac. Sci. Technol. B 12(1), Jan/Feb 1994, pp. 449-453 and J. Hopwood et al., "Mechanisms for highly ionized magnetron sputtering," J. Appl. Phys., Vol. 78, No. 2, Jul. 15, 1995, pp. 758-765. Further attempts to improve RF induced plasma processing by generating a greater percent of ionized sputtered material employing a coil having a generally flattened surface defined by parallel conductors is disclosed by Cuomo et al., U.S. Pat. No. 5,280,154.
Although electroless deposition and electroplating offer the prospect of low cost, high throughput, high quality plated films and efficient via, contact and trench filling capabilities, the requirement for a catalytic seed layer becomes problematic, particularly in filling high aspect ratio openings. Electroless plating generally involves the controlled autocatalytic deposition of a continuous film on the catalytic surface by the interaction in solution of a metal salt and a chemical reducing agent. Electroplating comprises the electrodeposition of an adherent metallic coating on an electrode employing externally supplied electrons to reduce metal ions in the plating solution. A seed layer is required to catalyze electroless deposition or to carry electrical current for electroplating. For electroplating, the seed layer must be continuous. However, for electroless plating, very thin catalytic layers, e.g., less than 100 .ANG., can be employed in the form of islets of catalytic metal
Electroless plating has been applied to the manufacture of optical disks. See for example, Kumisaka et al., U.S. Pat. No. 4,894,260.
It is very difficult to form a high conductivity interconnect pattern having high aspect ratio openings employing Cu or a Cu alloy, e.g., a Cu-base alloy, by electroless plating or electroplating, because sputtered catalytic seed layer materials particularly Cu, exhibits extremely poor step coverage, particularly for high aspect ratio openings, e.g., contact, via or trench openings of about 2:1 and greater. Such poor step coverage would inhibit electroplating due to discontinuities of the Cu seed layer, and inhibit electroless Cu deposition for failure of Cu to reach the bottom and lower side walls of high aspect ratio vias/contacts or trenches. In addition, Cu has poor adhesion to dielectric materials and requires encapsulation to prevent diffusion.
A solution to such problems was addressed in copending application Ser. No. 08/857,129, issued as U.S. Pat. No. 5,969,422 filed May 15, 1997 (Our Docket No. 1033-226), wherein a method for electroplating and electroless plating Cu is disclosed, comprising depositing a seed layer containing a catalytically active metal, such as Cu, alloyed with a refractory metal, prior to electroless plating or electroplating. In copending application Ser. No. 08/768,447 filed Dec. 18, 1996, an electroless deposition technique is disclosed comprising the use of a spray process in lieu of liquid immersion, wherein itemized droplets of an electroless plating solution are sprayed onto a substrate.
There are significant difficulties attendant upon the application of electroless plating and electroplating in the context of a semiconductor substrate, particularly for ULSI application. For example, during electroplating, metallic contact fingers are typically employed to provide electrical contact with a seed layer on a substrate. During the electroplating process itself, metal from the electroplating solution is disadvantageously electroplated on the contact fingers, thereby generating contaminating particles, as when the electroplated metal is delaminated from the contact fingers. In addition, electroplated metal on the contact fingers increases contact resistance resulting in a high voltage drop and failure.
A conventional approach to the problem of electroplating on contact fingers comprises frequent removal of electroplated metal from the contact fingers, as by wiping or etching, to improve the reliability of the electrical contact. Such approaches are inefficient and time consuming.
Another problem frequently encountered in electroless plating or electroplating a metal on a substrate is the undesirable electrodeposition of metal on the backside and on the edges of the substrate. A satisfactory solution to that problem has not yet surfaced in the art.
A conventional wafer plating is disclosed in U.S. Pat. No. 5,429,733, which issued on Jul. 4, 1995 to Ishida. In the plating device disclosed by Ishida, the lower surface of the circumferential edge of the wafer is restrained by a holding means onto a positioning base portion formed in an opening portion of a plating bath, and a plating fluid is applied onto the lower surface of the wafer. An air bag is employed as a holding means for downwardly depressing the wafer after plating. The air bag constrains only the upper surface of the circumferential edge of the wafer at an expanded state and releases the constraint by contracting to restore an initial configuration in a non-expanded state. The backside of the wafer and the edge of the wafer are not exposed to the plating solution. However, the wafer is not rotated. As a result, the plating thickness uniformity is reduced and the loss of the plating solution is increased since excess plating solution cannot be removed by wafer spinning.
Another wafer plating device is disclosed in U.S. Pat. No. 5,472,592, issued on Dec. 5, 1995 to Lowery. The apparatus disclosed by Lowery comprises a tank structure for containing an electrolyte and an anode. A shaft is rotatably mounted within the tank to rotate about a first axis. An arm is mounted on the shaft, and a fixture for receiving the substrate is rotatably mounted on the arm to rotate about a second axis, so that the substrate is both revolved about the first axis and rotated about the second axis. The fixture wheel carries the substrate to be plated, such as a semiconductor wafer, which is mounted by three spring loaded electrical contacts. Electrical contact is maintained between the rotating substrate and a stationary power supply for plating. A flat annular gasket is received within an annular recess formed in the front face of the fixture wheel to seal the back face of the wafer. A solid sheet gasket or another type of seal such as an O-ring seal, can also be used to seal the wafer backside. However, metal will be plated on the edge of the wafer as well as on the contact of the plating device described in U.S. Pat. No. 5,472,592.
Accordingly, there exist a need for an apparatus and efficient methodology for preventing the undesirable electroplating of metal on contact fingers in electrical contact with a seed layer on a substrate during electroplating. There also exists a need for an apparatus and efficient methodology for preventing undesirable electrodeposition of metal on the backside and edges of a substrate during electroless plating and electroplating on the front side of the substrate.